1. Field of the Invention
The present invention relates to circuit configurations and methods for controlling a data exchange in a circuit configuration.
2. Description of Related Art
Bus systems are often used for the purposes of data exchange in data processing systems (computer and microprocessor systems, control units, peripheral units and other information processing systems). One such bus system is the AMBA bus, including its variants AHB, ASB and APB (www.arm.com/products/solutions/AMBAHomePage.html). The AHB bus is a multimaster bus, in which individual masters are able to request the bus via a bus request. In the event of multiple requests, the arbiter decides which master the bus will be assigned to for its data transfer. The selected master addresses via an address a slave to which it may transmit data via a write bus or from which it receives data via a read bus. The data transmission may last for multiple clock cycles and is terminated by a ready signal, which releases the bus again for the next master request. For example, the CPU (central processing unit) or a DMA (direct memory access) could function as the master which retrieves data from a memory or transmits data to a peripheral unit. The transmission pathways are each controlled by an address, which may change constantly.
Another data transmission option is data routing, as described in PCT/EP2008/060493, which solves the problem of distributing data to configurable addresses (i.e., fixed at run-time). The available data from a data source are written in succession to a fixed address in a RAM (random access memory) from which the data sink (destination) retrieves the data cyclically. With each retrieval of data, the corresponding data region is marked as read and is thus free for the next data from the same source. This type of data distribution is advantageous when there is a fixed connection between a data source and a data sink and data are exchanged as often as desired.
In data exchange with the aid of an AMBA bus system, each master reports a request to the bus system and a decision is made by an arbiter as to which master the bus will be assigned to. The data transfer is therefore very flexible but also very complex. However, the (aforementioned) data routing is simpler because each participant is simply queried one after the other as to whether it has a request and they are then processed one after the other. Write requests and read requests for RAM are differentiated here. In a write request, data from the source are retrieved and written into the RAM exactly when the target address in the RAM is free. Conversely, data are processed in a read request only when the data are valid and the datum is marked as read during reading.
One disadvantage of this routing is that k cycles are needed for writing into the RAM for each data transfer from a source to a sink, and, in addition, I cycles are needed for reading out of the RAM. If n data sources and m data sinks are processed in succession, a run-through needs up to t=n*k+m*I cycles. If no request is present, the query of the source or sink is shortened to zero cycles. The cycle time, i.e., the time until the same source or sink is processed again, is thus dependent on the number of requests. The cycle time is too long for some applications and the variable cycle time is unfavorable for others.